In most of the semiconductor components, such as low power DRAM or some other low power memories just like 1T-SRAM, the voltage power sources (VPP) of their Word Lines are higher than the operation voltage (Vdd). For example, if Vdd=1.8V and VPP=2.8V, then there are one or more VPP Pumping Circuits to provide the high voltage on the word line.
The pumping circuit of the conventional memory is shown as FIG. 1. The NMOS (N Type Metal Oxide Semiconductor) capacitor 12 is the charging capacitor. The current source 11 of NMOS is used to provide the charge current. A clock signal θ1 is input to the inverter 13 to generates the clock signal θ2 for pumping the voltage VPP up to meet the high voltage for the word line need. The conventional memory pumping circuit operates well with the memory operation voltage Vdd=2.5V; but in the case of low power DRAM or 1T-SRAM in which the operation voltage is limited to 1.8V, the driving current will not guarantee these low power memories working on the normal operation. A method to improve the conventional drawback is by increasing the MOS capacitor area to make sure the driving current enough for the VPP output. But, increasing the area of the MOS capacitor will also increase extra manufacture cost. Therefore, this is not a good solution.